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Solving Constraint Satisfaction Problems on Neuromorphic Chips (Dynap-se)

Solving constraint satisfaction problems (CSPs) is a notoriously expensive computational task, for example, Sudoku, Boolean Satisfiability Problem, etc. In this work-group, we will build a network to solve some typical constraint satisfaction problems on neuromorphic chips.

To accelerate the searching of optimal solutions, we will utilize the randomness brought by the intrinsic noise on neuromorphic hardware.

We will first fit this network into one Dynapse board (4096 excitatory and inhibitory analog neurons in total). Then when the problem's scale is increased, we can scale the network up by using multiple Dynapse boards.

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Timetable

Day Time Location
Mon, 24.04.2017 15:00 - 00:00 Lab

References: 

1.  Binas, J. and Indiveri, G. and and Pfeiffer, M. Spiking Analog VLSI Neuron Assemblies as Constraint Satisfaction Problem SolversInternational Symposium on Circuits and Systems (ISCAS) 2094-2097, 2016

2.  Hesham Mostafa, Lorenz K. Muller, Giacomo Indiveri Recurrent networks of coupled winner-take-all oscillators for solving constraint satisfaction problemsNIPS, 2013

Leader

Dongchen Liang

Members

R B Benosman
Fatemeh Hadaeghi
Giacomo Indiveri
Dongchen Liang
VALERIO MILO
Mantas Mikaitis
Fredrik Sandin